1. Field of the Invention
The present invention relates to recessed transistors and methods of forming the same, and more particularly, to recessed transistors removed fences of a semiconductor substrate from sidewalls of a device isolation layer and methods of forming the same.
2. Description of Related Art
In recent years, semiconductor devices have been fabricated using a recessed transistor in order to increase the integration density of transistors on the semiconductor device and to overcome the limitations of a design rule. The recessed transistor includes a channel-portion hole, which is disposed between device isolation layers in a semiconductor substrate, and a gate pattern, which fills in the channel-portion hole. In this case, the channel region of the gate pattern filled in the channel-portion hole can have a larger dimension than a channel region of a planar-type gate pattern disposed on a semiconductor substrate.
However, although the gate pattern in the channel-portion hole may have a channel region with a larger dimension as compared to the channel region of the planar-type gate pattern, the recessed transistor is formed to have a fence in the semiconductor substrate on a sidewall of the device isolation layer. The fence of the semiconductor substrate may form a parasitic transistor in the channel of the active region along the sidewall of the device isolation layer during the drive process of the recessed transistor. Accordingly, before the channel region around the channel-portion hole is inverted, the parasitic transistor may invert the fenced-type channel region on the sidewall of the device isolation layer, thus lowering the current driving capability of the recessed transistor.
U.S. Pat. No. 6,825,526 to Yue-Song He et al. (the '526 patent) discloses a structure for increasing drive current in a memory array and related method. According to the '526 patent, the structure and method include forming insulation regions disposed in a semiconductor substrate, and forming a trench and a tunnel oxide layer, which covers the trench between the insulation regions. Thereafter, a channel region is formed below the tunnel oxide layer.
However, the structure and method disclosed in the Yue-Song He patent do not provide an effective way to further increase the dimension of the channel region while further reducing the design rule. This is because the trench can not simultaneously overcome a design rule between the insulation regions and increase a drive current in a memory array. This is in part because the channel region is restricted by the design rule between the insulation regions and formed in the semiconductor substrate adjacent to the trench. Accordingly, the structure and related method cannot continuously increase the drive current in the memory array while reducing the design rule.